1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including an adjusted circuit a slew rate (an amount of change in output voltage per unit time for step input) of whose output is dependent on a bias current and a circuit automatically adjusting the value of the bias current to achieve low power with proper slew rate.
2. Description of the Related Art
FIG. 9 is an illustration of bias adjustment to a prior art semiconductor integrated circuit 10X including an adjusted circuit 11 whose slew rate is dependent on a bias current IB.
To the adjusted circuit 11, the bias current IB is provided from a bias current 12. The output of the adjusted circuit 11 is connected to another circuit not shown or an output terminal of the semiconductor integrated circuit 10X and a load impedance measured at the output of the adjusted circuit 11 is ZL.
FIG. 10 shows a sample and hold circuit as an adjusted circuit 11 of FIG. 9, which is a combination of a switched capacitor circuit and an operational amplifier 13X. FIG. 10 shows a case where the load impedance can be approximated by a capacitance CL. FIG. 11 are waveform diagrams showing operation of the circuit of FIG. 10.
The switches of FIG. 10 are controlled by two phase clocks φ1 and φ2 shown in FIG. 11, wherein a high and a low of each clock correspond to ON and OFF of switches controlled by the clock. The switches P11, P12 and P13 are is controlled by the clock φ1 and switches P21 and P22 are controlled by the clock φ2.
The input and output voltages of the adjusted circuit 11 are denoted by Vi and Vo, respectively. When the clock φ1 is high, the both ends of a integrating capacitor C2 are grounded to be reset and a sampling capacitor C1 is simultaneously charged with the input voltage Vi. The electric charge Q1 charged on the sampling capacitor C1 is C1×Vi. Thus, when the clock φ2 goes high, the electric charge Q1 is transferred to the integrating capacitor C2 and if a sufficient settling time is given, the electric charge Q2 and if a sufficient settling time is given, the electric charge Q2 of the integrating capacitor C2 becomes C2×Vo. Since Q1=Q2, a relation to Vo=(C1/C2)Vi holds.
When the adjusted circuit 11 is operated with a high speed clock signal, unless the adjusted circuit 11 has a sufficient drive ability for the load capacitance CL, the slew rate is insufficient and Vo<(C1/C2)Vi, whereby a necessary output amplitude will not be obtained.
In design, the bias current IB to be provided to the operational amplifier 13X is determined such that a necessary slew rate can be obtained under the worst conditions of a power supply voltage, temperature and a deviation in circuit element characteristics occurring in fabrication process. Besides, there are taken into consideration a variation in drive ability of the operational amplifier 13X in company with a variation in the bias current IB and a variation in the capacitance CL.
In ordinary case, however, the worst conditions does not occur, thereby resulting in excessive power consumption.
FIG. 12 shows the output voltages Vo, with respect to time between t1 and t3 of FIG. 11, of adjusted circuits 11 under different conditions fabricated on the basis of the same design. In FIG. 12, VLL denotes the lowest limit value of a necessary output voltage Vo for ensuring a normal operation of the adjusted circuits 11 under the worst conditions.
Referring back to FIG. 9, in order to solve the problem of excessive power consumption, a configuration was adopted in the prior art in which a bias circuit 12 capable of adjusting the bias current IB is incorporated in the semiconductor integrated circuit 10X, a bias current IB having the same value as the bias current IB provided to the adjusted circuit 11 is taken out from the bias circuit 12 to the outside and measured with an ammeter 14, and such a trimming adjustment is performed that the bias current IB is adjusted by an adjustment circuit 15X to make the bias current IB within a given range. This adjustment is performed in the final stage of a fabrication process of the semiconductor integrated circuit 10X.
However, since characteristic variations in load impedance and a variation in load impedance caused by variations in power supply voltage and temperature are not taken into consideration, the bias current BI has to be determined assuming that the load impedance has the maximum value, leading to insufficient reduction in power consumption. Further, since adjustment operation for the bias current IB is necessary in fabrication process of the semiconductor integrated circuit 10X, the cost increases.